Chapter 5 Notes

Instruction Set Architecture Level

Compiler -> ISA -> Hardware

Backward compatibility big deal for Intel

Design Guide

	ISA instructions that can be implemented efficiently in current and future technologies
	Provide clean target for compiled code

ISA level code is what a compiler outputs

Memory Models

Common unit size is 8 bits -> byte

4 byte or 8 byte "words"

Words often aligned at natural boundaries

Linear address space vs. data/program space

Kernel mode vs. user mode

Registers control execution, hold temp results, etc.

	Special purpose -> SP, PC, etc.
	General purpose (RISC 32+)

PSW (program status word) flags register

	N, Z, V (overflow), C (carry), A (aux carray), P (parity)
	Machine mode, trace bit, CPU priority, interruptable...

Instructions

Data Types

Numeric

	Integer (2's complement), signed / unsigned
	Floating point / Decimal

Non-numeric

JVM

Instruction Formats

	Opcode Operand (address) 0, 1, 2, 3 address instructions
	Shorter better
	Memory bandwidth for fetching instructions still a problem
	Sufficient room in the instruction to express all desired operations
	Number of bits in address field? What does it address? byte, word?
	K bit opcode, N bit address (2^K operations, 2^N memory cells)
	Expanding opcode (pg 325)

JVM - Simple

	1 byte op code (256)
	Special 1 byte instructions for ILOAD, BIPUSH, ISTORE

Addressing

Operands

	ADD 2 sources, 1 destination (lots of bits)
	Use registers (address smaller (64 regs. = 6 bit address)
	Use destination same as source
	Use assumed destination (some reg.)
	Stack based, 0 registers

Address Modes

	Immediate, address is the value
	Direct, address point to data
	Register, address specifies a register
	Register Indirect, address specifies a register that holds an address
	Indexed Addressing, register + offset
	Based Indexed, two registers added (+ optional offset?)
	Stack Addressing

Flow of Control

Procedures -> stack frames

Co-routines -> Simulate parallel processing on a single CPU

Traps -> Automatic procedure call due to some exceptional condition. Programmer does not need to constantly check in code.

Interrupts

	Asynchronous to program execution, can occur any time, unrelated often to program logic
	Should be transparent - when completed the computer shold be return to prior state.
	Interrupts are often given priorities

Intel IA-65 (pages 388-396)

	Bundles - EPIC, Explicitly Parallel Instruction Computing, the compiler tells the CPU what can be executed in parallel.
	Conditional execution - every instruction is executed, at the end of the pipeline the instruction may be ignored.
	Speculative loads