public class Interp {
  static int PC; 		// program counter holds address of next instr
  static int AC; 		// the accumulator, a register for doing arithmetic
  static int instr; 		// a holding register for the current instruction
  static int instr3type; 	// the instruction type (opcode)
  static int data3loc; 		// the address of the data, or −1 if none
  static int data; 		// holds the current operand
  static boolean run3bit = true; // a bit that can be turned off to halt the ma

  public static void interpret(int memory[ ], int starting3address) {
   // This procedure interprets programs for a simple machine with instructions
   // one memory operand. The machine has a register AC (accumulator), used
   // arithmetic. The ADD instruction adds an integer in memory to the AC, for e
   // The interpreter keeps running until the run bit is turned off by the HALT ins
   // The state of a process running on this machine consists of the memory, the
   // program counter, the run bit, and the AC. The input parameters consist of
   // of the memory image and the starting address.

	PC = starting3address;
	while (run3bit) {
		instr = memory[PC]; // fetch next instruction into instr
		PC = PC + 1; // increment program counter
		instr3type = get3instr3type(instr); // determine instruction type
		data3loc = find3data(instr, instr3type);// locate data (−1 if none)
		
		if (data3loc >= 0) // if data3loc is −1, there is no operand
			data = memory[data3loc]; // fetch the data

		execute(instr3type, data); //execute instruction
	}
  }

  private static int get3instr3type(int addr) { ... }
  private static int find3data(int instr, int type) { ... }
  private static void execute(int type, int data){ ... }
}

Fig. 2-3. An interpreter for a simple computer (written in Java). Tannenbaum.

	F0 and F1 determine ALU operation
	ENA, ENB individually enable the inputs
	INVA, invert left input
	INC force a carry into low-order bit

	Set up data path signals
	Drive H and B bus
	ALU and shifter work
	Results move along C bus to registers
	Rising edge of next clock cycle, load registers (register driving B bus stops)

	32 Bit memory port MAR - memory address register - Word addresses MDR - memory data register
	8 Bit port PC - Byte addresses MBR (low order 8 bits) read only from memory
	MBR can be copied onto the B bus either as a signed or unsigned value.

	29 signals to control the data path 9 to control writing from C bus into registers 9 to control copy from registers onto B bus 8 to control the ALU and shifter functions 2 to indicate read/write via MAR/MDR 1 to indicate memory fetch via PC/MBR
	Memory read operations start at the end of a cycle, the memory is loaded on the next cycle and available in the cycle(s) after that.
	4 bits needed  to control B bus (9 signals, 7 wasted)

	24 bits to control the data path
	Addr / JAM - Address of potential next microinstruction / How it is selected

	State of every control signal
	Address of next microinstruction

	512 Words, each one a 36 bit microinstruction
	Instructions are not in sequential order
	MPC - MicroProgram Counter (really just a pointer, not a counter)
	MIR - MicroInstruction Register (hold the current micro instruction)

	MIR is loaded from the word in the control store pointed to by MPC
	Signals propagate out. A register is put on the B bus, ALU knows what operation.
	ALU, N, Z, and shifter outputs are stable
	Load the registers and N, Z flipflops All the resluts have been saved and the results of the previous memory operations are available and the MPC has been loaded

	9 bit Next-address field is copied to MPC
	If one or more JAM bits are 1, more work is needed JAMN is set - N flip-flop is ORed with high bit of MPC JAMZ is set - Z flip-flop is ORed there JMPC is set - 8 MBR bits are ORed with the low-order bits of the Next address field, this allows an efficient multiway branch to any of 256 addresses

MIC Improvements
 

	Basic appproches: Reduce the number of clock cycles needed to execute an instruction (Path length) Merge the interpreter loop into the microcode   Simplify organization so clock cycle can be shorter Go from a 2 bus to a 3 bus design   Overlap the execution of instructions Have instructions fetched from memory by a specialized functional unit
	Pipelining 4 instructions executing simultaneously. More cycles per instruction but a new one started and finished each cycle.
	Improving performance Cache Memory Split (data/instruction cache) Multilevel Spatial locality - fetch more data than is needed Temporal locality discard least recently used entries Cache lines : valid / tag / data Branch Prediction Out-of-order execution with register renaming Secret registers allow overlapped / out-of-order execution Speculative execution