Gate delay - signal propagation/switching delay
	Multiplexer - 2^n data inputs, one output, n control inputs to select one of the data input Parallel to serial conversion, data on input lines, step through all combinations of control lines outputting individual bits one at a time.
	Demultiplexer - routes single input to one of 2^n outputs depending on the control lines
	Decoder - n-bit number is input, selects exactly one fo 2^n output lines Memory bank selector
	Comparator - compares inputs for equality
	Shifter
	Adder Half adder Full adder Carry-select adder
	ALU bit slices all operations at once
	Clocks 1 to 500 mhz (1000 nsec. to 2 nsec.) sub cycles - insert a delay, phase shifting from the primary clock
	Latches & FlipFlops - Memory
	Memory (Fig 3-29) Three data inputs, two address inputs, Chip Select, RD (read/write?), OE (output enable) Three data outputs 4 X 3 Memory (4 words of 3 bits each)   To extend to 4 X 8 add five more columns of four flip-flops each, five more input lines and five more output lines. What is required to go to a 8 X 3? RAM (DRAM - FPM, EDO   SDRAM) ROM, PROM, EPROM, EEPROM, Flash Memory Modern CPUs on a single chip Pins - address, data, control Control pins - Bus control, Interrupts, bus arbitration, coprocessor signaling, status, misc. Bus Width Clocking Arbitration Operations Pentium II Ultra Sparc II picoJava II (page 179) Example Buses: ISA, EISA, PCI, USB (pg. 189) Interfacing (I/O chips) UART, PIO Address decoding